| 型号 | 厂家 | 描述 | 大小 | 页数 | 厂家标志 |
|---|---|---|---|---|---|
| NB6N239SMNR2G | ON SEMICONDUCTOR | 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT ±1/2/4/8, ±2/4/8/16 Clock Divider | 175 KB | 12 |  |
| NB6L11MMNG | ON SEMICONDUCTOR | 2.5V / 3.3V 1:2 Differential CML Fanout Buffer Multi−Level Inputs w/ Internal Termination | 84 KB | 9 | |
| NB6N239SMN | ON SEMICONDUCTOR | 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT ±1/2/4/8, ±2/4/8/16 Clock Divider | 175 KB | 12 | |
| NB6L239MNR2 | ON SEMICONDUCTOR | 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider | 104 KB | 13 | |
| NB6L14MMNR2G | ON SEMICONDUCTOR | 2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer | 154 KB | 11 | |
| NB6L239MN | ON SEMICONDUCTOR | 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider | 104 KB | 13 | |
| NB6L239MNR2G | ON SEMICONDUCTOR | 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider | 104 KB | 13 | |
| NB6L295MMNTXG | ON Semiconductor | 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs | 194 KB | 13 |  |
| NB6L611MNG | ON SEMICONDUCTOR | 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer | 146 KB | 9 | |
| NB6L14MMNG | ON SEMICONDUCTOR | 2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer | 154 KB | 11 | |
| NB6L14MNR2G | ON SEMICONDUCTOR | 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer | 113 KB | 10 | |
| NB6L11DR2 | ON SEMICONDUCTOR | 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator | 212 KB | 12 | |
| NB6L72MMNR2G | ON SEMICONDUCTOR | 2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with CML Outputs | 149 KB | 10 | |
| NB6L72MMNG | ON SEMICONDUCTOR | 2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with CML Outputs | 149 KB | 10 | |
| NB6L11D | ON SEMICONDUCTOR | Evaluation Board Manual for High Frequency SOIC 8 | 202 KB | 20 | |
| NB6L16DTR2 | ON Semiconductor | 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer | 120 KB | 12 | |
