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型号 厂家 描述 大小 页数 厂家标志
NB4L858MFAG ON SEMICONDUCTOR 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination 98 KB 10
NB4N11MDTG ON SEMICONDUCTOR 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination 98 KB 10
NB4L339MNR4G ON SEMICONDUCTOR 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination 98 KB 10
NB4N121KMNG ON SEMICONDUCTOR 3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output 107 KB 10
NB4N111KMNR4G ON SEMICONDUCTOR 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output 138 KB 10
NB4L16MMN ON SEMICONDUCTOR 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination 919 KB 12
NB4N1158DTR2G ON SEMICONDUCTOR Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA 102 KB 8
NB4N11SMNR2G ON SEMICONDUCTOR Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA 102 KB 8
NB49 ON SEMICONDUCTOR Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA 102 KB 8
NB4N111KMNG ON SEMICONDUCTOR 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output 138 KB 10
NB4L339MNG ON SEMICONDUCTOR 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer 176 KB 12
NB4N316MDTR2G ON SEMICONDUCTOR 3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis 206 KB 12
NB4N527SMNR2G ON SEMICONDUCTOR 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination 109 KB 10
NB4N11SMNG ON SEMICONDUCTOR 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination 109 KB 10
NB4L16MMNR2G ON SEMICONDUCTOR 2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination 919 KB 12
NB4L52MNR2G ON SEMICONDUCTOR 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination 135 KB 8
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